1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems in which data packets are transferred between a packet transmitter and a packet receiver. It is known to provide data processing systems in which data packets are transmitted between a packet transmitter and a packet receiver. Example forms of such systems may be employed for the transmission of data within system-on-chip integrated circuits.
2. Description of the Prior Art
It is known to design system-on-chip integrated circuits by connecting together a plurality of functional circuit blocks using interconnect circuitry. As an example, the functional circuit blocks may include a processor core, a graphics processing unit, a memory controller, input/output interface circuitry etc. The interconnect circuitry may have the form of a wide parallel signal connection in which a plurality of multi-bit channels are provided passing in each direction. An example of such an interconnect architecture is the AXI interconnect architecture designed by ARM Limited of Cambridge, England. A problem with this approach as system-on-chip integrated circuits increase in complexity and size is that the parallel interconnect circuitry may include a disadvantageously large number of signal lines which can require routing over long distances within the system-on-chip integrated circuit thereby consuming a disadvantageous amount of circuit area and resource.
In order to address the above problem of routing wide parallel interconnect circuitry over relatively large distances within a system-on-chip integrated circuit, it has been proposed to convert the parallel signals at the source into a plurality of data packets which can then be serially transmitted over a narrower interconnect. As an example, a full parallel interface of over 100 signal lines may be broken down into a plurality of narrower multi-bit data packets which are each transferred in turn in a time-division-multiplexed fashion over a narrower interconnect before being reassembled at the packet receiver into the full width parallel interface signals and applied to the destination circuitry.
It is known within some systems that the data source and the data destination may be operating in different clock domains. For example, a system-on-chip integrated circuit may include multiple clock domains using clocks of different frequencies. Some of the frequencies may vary depending upon the performance requirements of the circuitry within that domain at a particular point in time e.g. a processor core may have its clock frequency varied depending upon the processing workload it currently faces with a lower clock frequency being used when the workload is low in order to reduce power consumption. An additional complication is that the clocks used to control the circuitry within different clock domains may be asynchronous from one another. This imposes a difficulty in passing data packets and associated control signals between the different clock domains with their asynchronous clock signals.
One way of dealing with passing signals between asynchronous clock domains is to provide first-in-first-out buffers between the clock domains into which signals can be captured for resynchronising with the clock signal of the destination clock domain. A problem with this approach is the circuit area and resource consumed by the need to provide such first-in-first-out buffers for all of the signals crossing the asynchronous clock boundary. As well as the data packets themselves which pass between the packet transmitter and the packet receiver across the asynchronous clock boundary, there are other control signals which need to be passed across this asynchronous clock boundary. One such control signal is a token signal which indicates to the packet transmitter whether or not there is storage capacity within an associated first-in-first-out buffer. This token can be used as part of a flow control system that provides “back pressure” between the packet transmitter and the packet receiver so as to gate the packet transmitter from sending more data packets when there is insufficient storage capacity within a receiving first-in-first-out buffer to store those data packets for resynchronisation across the asynchronous boundary. As the token itself must pass across the asynchronous clock boundary, it must also be provided with its own first-in-first-out buffer so it can be synchronised with its target clock domain.
Another feature of such systems exchanging data packets is that multiple channels may share the same packet transmission mechanism. Examples of such different channels would be a write address channel, a read address channel, a write data channel, a read data channel and a write response channel. Wide parallel signals on each of these channels may be broken down into a plurality of narrower data packets which are then time division multiplexed across the same data packet transmission circuits before being reassembled at the destination into their different respective channels. The packets from each of these channels will be consumed into their own first-in-first-out buffer for resynchronisation to the destination clock domain. Thus, the number of first-in-first-out buffers required increases and the resources consumed by those buffers similarly increases. This problem is further compounded when multiple virtual channels are supported. For example, multiple instances of the above mentioned five different channels may be supported with each of these instances corresponding to a respective virtual channel which may routed between a different pair of a source and a destination, but all crossing the same asynchronous clock boundary. The increase in the circuit resources required when multiple channels and multiple virtual channels are supported also applies to the control signals which pass the information back to the source of the data as to whether or not there is buffer storage capacity at the destination. These control signals (so called credits or tokens) which are passed back to the source also require their own buffers as previously mentioned. Separate tokens are needed for each of the different channels and each of the different virtual channels such that there is a rapid growth in the circuit resource required to pass these flow control signals between asynchronous clock domains.
One standard form of flow control signal is one using a token passing flow control mechanism. A token is associated with each unit of storage capacity within the destination buffer. As the source transmits a data packet to the destination, it decrements a count of the number of tokens available at the buffer. As the buffer empties a data packet it generates a token which is sent back to the source and used to increment the source token count. If the source token count indicates that no more storage capacity is available within the buffer, then no data packets are sent until a token is received indicating that storage capacity has become available within the buffer. More than one data packet may be emptied from the buffer in any time period and accordingly the system includes the capability to send signals indicating that multiple tokens should be applied to the source count at one time. The source side thus keeps a count of how much storage capacity is available at a destination buffer at a given time and accordingly does not overflow that buffer in a manner which may cause a data packet to be lost.
One superficially attractive possibility for decreasing the amount of circuit resource required to pass back the token count data to the source would be for the multiple channels to share a buffer for passing this token count data across the asynchronous clock boundary back to the source. However, a problem with this approach is that it introduces a dependency between the different channels in a manner which can degrade overall performance and, in some pathological cases, could lead to a deadlock. As an example, one of the channels may fill all of the buffer resources required for passing token data back to the source leaving the other channels unable to pass token data back to the source, thus stalling those other channels when in fact they do have buffer capacity able to receive new data packets. A further problem with this superficially attractive approach is that the buffer that is shared for the passing of token data back to the source should be sized for the combination of worst case situations that can arise across all of the channels which share that buffer. Thus, the saving in resource by sharing this buffer is reduced.